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JPS5690692A Expired / Lapsed JP ⏱️ 0.0 years remaining

Signal processing system of electronic switch board

Assignee: NEC Corp
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Filing: 1979-12-24
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Granted: —
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Expires: 1999-12-24
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Abstract

Abstract PURPOSE:To enable reduction in load on a processing system, especially, priority processing such as processing of an important call during abnormal convergence and disconnection and response processing, by prescribing the priority level of input data at a processor side by a queue number. CONSTITUTION:A register input is inputted to memory 2 via signal line 1 and further written in memory 6 through processor 5. According to the kind of the input signal and the kind of a change, signal processor 5 adds the detection signal of the register input change to each corresponding queue 7 successively. The output signal of main processor 9 is converted by decoder 8 into the read signal of each queue 7 and data is read out of each queue 7. This read data is supplied to main processor 9 via selector 10. With this data, main processor 9 performs data processing. Then, using different scanning periods gives a read of each queue 7 a priority level.

Inventors

  • 👤 Masakatsu Kuroki
  • 👤 Susumu Iwasaki

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-02 22:12
CPC Classifications
H; H04; H04M; H04M3/00; H04M3/22; H04M3/36; H04M3/365

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