Repeater for digital communication

Abstract

Abstract PURPOSE:To prevent accumulation of jitter, by setting t1>>t2 or t1<<t2 when the delay time from the equalizer to the discriminating circuit and the delay time from the equalizer to the discriminating circuit through the timing extracting circuit are denoted as t1 and t2 respectively. CONSTITUTION:The digital signal is input to discriminating circuit 9 and timing extracting circuit 8 through equalizer 6. The output of timing extracting circuit 8 is input to discriminating circuit 9 through delay circuit 11. At this time, t1>>t2 or t1<<t2 is set when the signal delay time from equalizer 6 to discriminating circuit 9 and the signal delay time from equalizer 6 to discriminating circuit 9 through timing extracting circuit 8 and delay circuit 11 are denoted as t1 and t2 respectively. Thus, the recurrent action of systematic jitter is reduced by inserting delay circuit 11 to delay the clock signal by several time slots or more.

Inventors

• 👤 Takatoshi Minami

Bibliographic Details