Semiconductor memory device

Abstract

Abstract PURPOSE:To enhance the integrity and the performance of the semiconductor memory device by forming the device of ordinary MOS transistors and MOS transistors having two layer gate electrode. CONSTITUTION:The first MOS transistor Q11 having ordinary configuration and the second MOS transistor Q12 having two-layer gate electrode are formed on the same semiconductor substrate, the source of the tansistor Q11 is connected to the first gate electrode layer of the transistor Q12, and the connector is used as an information memory anode. The first and second bit lines BL1 and BL2 selected by the addresses in column direction are connected to the drains of the transistors Q11 and Q12 respectively, the first and second word lines WL1 and WL2 selected by the addresses in row direction are connected to the first and second gate electrodes of the transistors Q11 and Q12 respectively, and a power source voltage B is connected to the source of the transistor Q12. Thus, the transistor Q12 is conducted or shut off corresponding to the information ''1'' or ''0'', and operated to read as prescribed.

Inventors

• 👤 Kenji Natori

Bibliographic Details