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JPS566568A Expired / Lapsed JP ⏱️ 0.0 years remaining

Sampling method for facsimile signal

Assignee: Sanyo Electric Co Ltd
•
Filing: 1979-06-28
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Granted: —
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Expires: 1999-06-28
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Abstract

Abstract PURPOSE:To reproduce a good picture which is free from the jitter effect, by selecting the two sets of sampling clocks having the different phases and then setting the varying point of the picture signal at the center of the sampling timing. CONSTITUTION:The picture signal extracted out of demodulator circuit 10 receives the shaping into the binary coded signal through waveform shaping circuit 11 to be then sent to sampling clock comparator circuit 2. Circuit 2 supplies the oscillation signal of oscillator circuit 13 to clock signal generating part 21 to produce pulse- type two sampling clocks S1 and S2 having the 180 deg.-phase difference plus sample signals J and K each. These clocks and signals are applied to AND circuits 21 and 22 along with picture signal varying point detecting output signal d of varying point detecting part 24. Then picture signal d near the varying point is sampled, and detection signals L1 and L2 are sent to clock selection circuit 4 through circuits 21 and 22. Here selected clock S1 or S2 plus signal d are applied to sampling circuit 14. As signal d is positioned at the area near the middle of S1 and S2, no effect of jitter is given at all by the selection of S1 or S2. This output is then applied to recording circuit 16 via interface circuit 15.

Inventors

  • 👤 Hideji Yanase
  • 👤 Koji Ueda
  • 👤 Mitsugi Ikeda

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-10-31 22:24
CPC Classifications
H; H04; H04N; H04N1/00; H04N1/40

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