Semiconductor integrated circuit system

Abstract

Abstract PURPOSE: To reduce a test time by a method wherein timing signals are supplied to each function part by means of a signal selection circuit and thus, reducing the number of test steps during a function test time. CONSTITUTION: Each of data multiplexers 10W14 is inserted in each route of a timing signals which are sent from a timing signal generation circuit 9 to a bus buffer 1, a memory 4, a program counter 5, an A register 7, and a B register 8, respectively, and then, a timing signal from the timing signal generation circuit 9 is supplied to an input terminal of each of data multiplexers 10W14 and another timing signal is supplied to the other input terminal, thus, making the bus buffer 1 or the B register 8 operate by means of two system timing signals, respectively. COPYRIGHT: (C)1981,JPO&Japio

Inventors

• 👤 Tsutomu Miyazaki
• 👤 Sumitoshi Shirasaka

Bibliographic Details