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JPS5664460A Expired / Lapsed JP ⏱️ 0.0 years remaining

Semiconductor device

Assignee: Mitsubishi Electric Corp
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Filing: 1979-10-30
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Granted: —
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Expires: 1999-10-30
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Abstract

Abstract PURPOSE:To reduce the occupying area of a resistor in a semiconductor device by utilizing the isolating conductivity of a nitride film or an oxide film as a load resistance when integrating an FET or a bipolar transistor and a load resistor. CONSTITUTION:A thick field SiO2 film 2 is formed on the periphery of an Si substrate 1, reverse conductivity type diffused regions 3, 4 are formed in the substrate 1 surrounded by the film 2, and a thin gate SiO2 film 5 and a polycrystalline silicon gate electrode 6 are sequentially coated on the surface of the exposed substrate 1 between the regions 3 and 4 as an FET. Subsequently, the whole surface is covered by a thick insulating film 9, a window is opened thereat. When aluminum wire 10 is mounted to the regions 3, 4 and the electrode 6, a thin film 11 made of Si3N4 or SiO2 or the like is formed at the outside of the aluminum wire 10 formed on the region 2 or the like as a load resistance simultaneously integrated, and is used as the load resistance. Since the resistance is thus provided at the contact part of the electrode, there can be provided an inverter having small occupying area.

Inventors

  • 👤 Kazushi Nagata

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-01 12:15
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/80; H10D84/811; H10D84/817

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