JPS5651087A
Expired / Lapsed
JP
⏱️ 0.0 years remaining
Refresh control system
Assignee: Casio Computer Co Ltd
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Filing: 1979-10-02
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Granted: —
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Expires: 1999-10-02
Abstract
Abstract PURPOSE:To enable to refresh RAMs surely with a simple circuit constitution, by giving priority to the refresh operation according to the refresh request signal than the memory cycle operation. CONSTITUTION:When a refresh request signal is fed to a RAM system, a WAIT signal is fed to a CPU1 from a system 2. Thus, the memory cycle operation in the CPU1 is extended to gieven priority over the RAM of the system 2 than the memory cycle operation. Accordingly, the refresh control of RAMs can be ensured with a simple circuit constitution such as the stop of clock of memory cycle operation and whether or not in memory cycle.
Inventors
- 👤 Kiyoshi Iezuka
Bibliographic Details
Application Number
—
Jurisdiction
JP
Data Source
google_patents
Last Synchronized
2026-11-03 06:27
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/406
Claims Analysis
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References Cited (Backward Citations)
JPS4991136A
Cited
JPS5391637A
Cited
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