Memory unit

Abstract

Abstract PURPOSE: To make it possible to ignore apparently the delay of an operation speed accompanying error detection as to continuous write or read operation, by providing a memory part of two stages of access registers. CONSTITUTION: In write operation, address data from CPU10 are temporarily held by 2nd address register 12 by way of 1st address register 11 and write data are passed through 1st data input register 13 and Hamming code generator 15 to held the data and its check code in 2nd data input register 16 temporarily. Then, the contents of register 16 are written at assigned addresses of memory part 21 and this operation is repeated to finish write operation. In read operation, data and its check code are read out of memory part 21 in accordance with addresses supplied from CPU10 by way of registers 11 and 12 and then stored in 1st data output register 20 and on the basis of the code, they are stored in 2nd data output register 17 after an error check on the data, thereby sending them to CPU10 afterward. COPYRIGHT: (C)1981,JPO&Japio

Inventors

• 👤 Kazuya Shibazaki

Bibliographic Details