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JPS5629362A Expired / Lapsed JP ⏱️ 0.0 years remaining

Semiconductor dynamic memory

Assignee: Individual
•
Filing: 1979-08-20
•
Granted: —
•
Expires: 1999-08-20
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Abstract

Abstract PURPOSE:To obtain a high integrity memory device by a VMOS technique by forming an N type memory region on a P<-> type epitaxial layer on a P<+> type Si substrate by self-diffusion with its density of P<+>>N>P<->. CONSTITUTION:B is selectively added to a P<+> type Si substrate added with P and a plane <100>, and a P<-> type epitaxial layer 3 is laminated thereon. At this time a thin N type memory region 2 is formed owing to the difference of rediffusion of the P and the B. Then, an N<+> type bit region 4 is formed on the upper portion of the region 2, an SiO2 film 5 is coated thereon, an opening is perforated at the film 5, is anisotripically etched to form a V-shaped groove 6 to divide the regions 4 and 2 into two. Since the layer 2 is thin and has no punch-through therebetween, the V- shaped groove may be reduced to improve the integrity. Subsequently, an SiO2 film 7 is coated on the oblique surfaces of the groove, and a polysilicon word line 8 is formed thereon. The junction capacity between the N type layer 2 and the P<+> type substrate stores charge, so that the oblique surfaces of the groove under the work line 8 becomes the N type channel of the VMOST. This configuration can obtain a high integrity and preferable area efficiency in memory cell.

Inventors

  • 👤 Shoichi Tanaka

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-01 17:33
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/34

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