← Back to Patent Explorer
JPS5628531A Expired / Lapsed JP ⏱️ 0.0 years remaining

Noise reducing circuit

Assignee: Faurecia Clarion Electronics Co Ltd
•
Filing: 1979-08-15
•
Granted: —
•
Expires: 1999-08-15
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract PURPOSE:To reduce white noise, by utilizing the pulsed noise eliminating function to control the frequency characteristic by the white noise level. CONSTITUTION:Noise detecting circuit 9 detects noise components included in the coming stereo signal and generates a trigger pulse signal during the time of existence of noise components, and short switch circuit 10 is turned off by this signal, and noise components taken out by phase inverting circuit 2 and stereo signal stopping circuit 3 are synthesized to the stereo signal including noise by synthesizing variable resistor 5, thereby eliminating noise components. Meanwhile, when pulsed noise is not detected, switch circuit 10 is closed, and the AGC voltage in noise detecting circuit 9 controls electronic control-system variable resistance circuit 16, which is inserted to the input side of switch circuit 10, to change the frequency characteristic, thus reducing white noise.

Inventors

  • 👤 Kiyoshi Amasawa
  • 👤 Seiji Mori
  • 👤 Takashi Taniyama

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-10-25 10:57
CPC Classifications
H; H03; H03G; H03G5/00; H03G5/16; H03G5/18

Claims Analysis

Total Claims: 0
No claims parsed yet. Click Sync Now above to re-index claims from Google Patents.

References Cited (Backward Citations)

No citation records indexed.

USPTO Annuity & Maintenance Windows

Maintenance schedule is calculated for granted US utility patents.

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag