Control system of array processor

Abstract

Abstract PURPOSE: To ensure an effective processing for two types of operations, by by- passing the output side of the mask pipe line MPL of one side at several arithmetic process parts having both the operation pipe line and the mask pipe line MPL to the input side of the MPL of the other side. CONSTITUTION: When the ADD instruction is set to addition instruction execution register 1, the set of the data elements and the mask bits (Ai, Bi, Mi), where i means 1... n, is supplied successively to addition pipe line 9 and MPL9a. Then the sum of the data elements Ai+Bi plus mask bit Mi are delivered from pipe lines 9 and 9a each to be sent to designated vector register 5. At the same time, bit Mi is sent to MPL10a through by-pass circiut part BP. When bit Mi is supplied to MPL10a, elements Ai' and Bi' of the vector designated by the 2nd and 3rd operands R 2 ' and R 3 ' of the MULTIPLY instruction are sent to multiplication pipe line 10. As a result, both the addition and the multiplication can be carried out simultaneously via the same mask register 6. COPYRIGHT: (C)1981,JPO&Japio

Inventors

• 👤 Masanori Mogi

Bibliographic Details