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JPS56137401A Expired / Lapsed JP ⏱️ 0.0 years remaining

Process controller

Assignee: Toshiba Corp
•
Filing: 1980-03-29
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Granted: —
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Expires: 2000-03-29
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Abstract

Abstract PURPOSE:To prevent the misoutput and to make output control with high reliability, by outputting the control signal to be changed twice from the CPU and changing the output of the output circuit only when the control signal is detected at the output circuit continuously twice. CONSTITUTION:When one write-in data A1 is output from CPU7, the stored content of the temporary storage circuit 9 for data is changed from A0-A1 in the timing given with the write-in signal B, and the output C is changed from A0-A1. The signal A1 and the signal C are given to the comparison circuit 10, and the coincidence signal D is given to the AND circuit 11. At this time, since write-in signal B is not given to the circuit 11 and no output is obtained from the circuit 11, the output F of the output data storage circuit 12 is given to the device 13 to be controlled as A0. A signal is fed to the circuit 11 only after the 2nd A1 is output from CPU7, and the output A1 is fed to the device 13 from the circuit 12 with the output E of the circuit 11.

Inventors

  • 👤 Takeo Toda

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-06 10:27
CPC Classifications
G; G06; G06F; G06F11/00

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