Manufacturing of 1-transistor type memory cell

Abstract

Abstract PURPOSE:To improve S-N ratio in a memory cell, by separately providing an n layer on a capacity section of a p type substrate and providing an electrode through an insulating membrane, and also by providing, in a switching FET section, an n layer on a gate insulating membrane with the electrode as a mask. CONSTITUTION:After a gate oxide membrane 2 was formed on a p type substrate 1, ion is selectively driven in a MIS capacity forming section to provide n layer 5. Gate electrodes 6 and 7 are formed by an electric conductive poly Si on the membrane 2, and an n<+> type drain and source are formed with these as masks. In this mechanism, the storing MIS capacity becomes depletion type, and when ''1'' level of the storing voltage is set to VDD and a threshold value of FET is set to VT, read voltage becomes higher by VDD/VDD-VT, and therefore, S-N ratio is improved. If another p<+> layer is added to the bottom of the channel layer 5, the read voltage can be further improved.

Inventors

• 👤 Shinji Shimizu

Bibliographic Details