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JPS5612129A Expired / Lapsed JP ⏱️ 0.0 years remaining

Synthesizer type receiver

Assignee: Panasonic Holdings Corp
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Filing: 1979-07-10
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Granted: —
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Expires: 1999-07-10
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Abstract

Abstract PURPOSE: To constitute a receiver of superior frequency stability whose reception frequency is variable at random frequency intervals by frequency-dividing the output of an oscillator under the control of the 2nd PLL circuit and by performing conversion into the 2nd intermediate frequency with its output. CONSTITUTION: An arrival signal from antenna 1 is converted into the 1st intermediate frequency by frequency mixer 4 with the output of the 1st local oscillator 5 of the 1st PLL circuit 28, and it is applied to frequency mixer 8 by way of the 1st intermediate frequency amplifier. The output of oscillator 11 of the 2nd PLL circuit 29, on the other hand, is divided by M at frequency divider 10 and higher harmonics are extracted by filtering at low-pass filter 9 and then supplied to and converted by frequency mixer 8 into the 2nd intermediate frequency. Maximum frequency intervals at which the output of frequency divider 10 is variable are equalized to minimum frequency intervals at which the output of the 1st local oscillator 5 is variable and dividing ratios of dividing-ratio setting circuits 21 and 25 are brought under the coupling control of dividing-ratio arithmethic circuit 22. COPYRIGHT: (C)1981,JPO&Japio

Inventors

  • 👤 Kiyotake Fukui
  • 👤 Shuichi Ninomiya
  • 👤 Tsuneo Danno

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-02 11:54
CPC Classifications
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