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JPS5611698A Expired / Lapsed JP ⏱️ 0.0 years remaining

Storage unit

Assignee: NEC Corp
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Filing: 1979-07-09
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Granted: —
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Expires: 1999-07-09
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Abstract

Abstract PURPOSE: To decrease the number of error corrections and to prevent the lowering in the performance of storage unit, by inverting and rewriting in the readout data at error detection and using the readout data from the same address through re-inversion after that. CONSTITUTION: When an error is detected, the set of new data to the register of the operation circuit 7, address register 9, and trace register 10 is suppressed with the error detection circuit 13. Simultaneously, the switching circuit 5 selects the signal line 106 via the error correction circuit 14 and the correction signal from the circuit 14 is inverted at the inverting logic circuit 15. This inversion signal is rewritten in the storage unit 1 via the switching circuit 12. In this case, corresponding to the address written in, the write-in of the inversion indication bit 4 is changed from 0 to 1. When these processings are finished, the suppression by the circuit 13 is reset, and the readout data from the address rewritten based on the state of the bit 4 after that is re-inverted at the switching circuit 3, allowing to make absent errors in data, thereby reducing the number of error corrections and preventing the lowering in the performance of the memory unit. COPYRIGHT: (C)1981,JPO&Japio

Inventors

  • 👤 Hideshi Ishii

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-10-31 17:31
CPC Classifications
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References Cited (Backward Citations)

JPS5318925A Cited

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