← Back to Patent Explorer
JPS56111185A Expired / Lapsed JP ⏱️ 0.0 years remaining

Semiconductor integrated memory cell

Assignee: NEC Corp
•
Filing: 1980-02-05
•
Granted: —
•
Expires: 2000-02-05
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract PURPOSE:To establish the static memory cell of samll size and low power, by giving the automatic refresh function to one transistor type dynamic RAM with IGFET, gate contage control capacitance and diodes. CONSTITUTION:One transistor dynamic RAM is formed with IGFETT2 forming storage capacitance, and IGFETT1 connected to the word and dot lines W and B, and when the storage by FETT2 is at 1 and the node N1 is at high level, IGFETT30 is ON and the charge is injected to the gate electrode of a gate voltage control type capacitance CG. Further, when the refresh signal line R is at high level, precharge by the electrode of the capacitance CG in higher level than the storage electrode of FETT2 through capacitance coupling via diodes D. On the other hand, when the storage by FETT2 is at 0, FETT1 is conductive and no charge supply is made. Through the provision of automatic refresh function to one transistor type dynamic RAM, the static memory cell can be of small size and low power.

Inventors

  • 👤 Tadahide Takada

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-04 19:09
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/402

Claims Analysis

Total Claims: 0
No claims parsed yet. Click Sync Now above to re-index claims from Google Patents.

References Cited (Backward Citations)

JPS5152745A Cited

USPTO Annuity & Maintenance Windows

Maintenance schedule is calculated for granted US utility patents.

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag