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JPS56103447A Expired / Lapsed JP ⏱️ 0.0 years remaining

Dicing method of semiconductor wafer

Assignee: Toshiba Corp
•
Filing: 1980-01-22
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Granted: —
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Expires: 2000-01-22
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Abstract

Abstract PURPOSE:To prevent propagation of a crack caused by bicing by a method wherein steps are formed along a dicing groove of the wafer, or a layer of a different kind of substance is formed on a dicing line. CONSTITUTION:The crack produced on the groove side at dicing the wafer is propagated in the direction rectangular to that of a maximum stress and repressed to make no further progress due to the formations of a step 5 and a notch 6 in the direction of the proceedings. Namely, the crack X starting from the groove 2 advances in the direction rectangular to the groove 2, and due to the situation of a step 4 at a position (a), a stress concentration arises between the positions (a), (b) to change a course of the crack to be directed toward the wafer surface, when the heat of the crack reaches the position (b). Therefore, the step 4 can control the range of the crack produced within the extent of the position, (a). Further, even when the Si substrate of the SiO2 film or the like and a different material 8 are piled, a similar phenomenon occurs to enable the propagation of the crack to be prevented. The extents of the step and notch are selected depending upon a substrate material, different kind of a material to cover, working condition and tools and the like.

Inventors

  • 👤 Masayasu Abe
  • 👤 Masafumi Miyagawa
  • 👤 Toshio Yonezawa
  • 👤 Hatsuo Nakamura

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-10-29 18:33
CPC Classifications
H; H10; H10P; H10P52/00; Y; Y10; Y10S; Y10S148/00; Y10S148/028; Y10T; Y10T225/00; Y10T225/10; Y10T225/12; Y10T29/00; Y10T29/49; Y10T29/49789; Y10T29/4979; Y10T29/49792

Claims Analysis

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References Cited (Backward Citations)

JPS4976467A Cited
JPS501312U Cited
JPS504549A Cited
JPS52155062A Cited

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