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JPS56103443A Expired / Lapsed JP ⏱️ 0.0 years remaining

Production of element isolation structure for semiconductor device

Assignee: NEC Corp
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Filing: 1980-01-21
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Granted: —
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Expires: 2000-01-21
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Abstract

Abstract PURPOSE:To achieve integration at a high level by forming an oxide for isolating elements preventing infiltration into the element region. CONSTITUTION:An Si3N4 film 23 is laid on an SiO2 film 22 on a P type Si substrate and with a resist mask applied, the films 23 and 22 and the substrate surface are etched sequentially. Then, after the removal of the resist, B ion is injected to form a P<+> layer 26. Then, covered with a poly Si27, a thermal oxide film 28 is formed and a resist mask 29 is applied. The SiO2 film 28 and the body poly Si27 are etched sequentially thereby making the surface of the Si3N4 film 23' almost flush with the end face of the poly Si layer 27'. Subsequently, the SiO2 film 28' is etched and the poly Si27 is oxidized completely to form a thick SiO2 film 27a in a nonelement region. Thus, an isolation layer is completed. With such an arrangement, a step is formed between a P<+> channel stopper and an N layer formed in the element region thereby allowing less floating capacity. This prevents bird beak to form a highly integrated semiconductor device.

Inventors

  • 👤 Toshiyuki Ishijima

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-10-30 17:53
CPC Classifications
H; H10; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/012; H10W10/0121; H10W10/0125; H10W10/0126; H10W10/10; H10W10/13

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