Insulated-gate field-effect transistor

Abstract

Abstract PURPOSE: To obtain a FET with short channel easily and also a large mutual inductance without enlarging the area by determining the channel length by controlling the width of an epitaxial layer and the depth of impurity diffusion. CONSTITUTION: On an n-type semiconductor substrate 10, a laminate of epitaxial layers of p, n, p, n, 11∼14 are grown. By operating anisotropic etching, V-shaped depressions 15 and 16 are cut into substrate 10. Next, while only the surface of depression 16 is being exposed, depression 15 and the top part are covered with oxide film 17. By using film 17 as a mask, a p-type impurity is diffused on the wall surface of depression 16, and thereby the function of a channel stopper is provided. Subsequently, on the bottom of depression 15, where it is intended to form a dual gate structure, the 1st gate 20, made of polycrystalline Si, is formed via oxide film 18. On top of this and expanding from the wall surface to the top part of film 18, polycrystalline the 2nd gate 22 is provided. Next, polycrystalline electrode wiring 24 is fitted to the 1st gate 20, and electrode 25 is provided in depression 16. COPYRIGHT: (C)1980,JPO&Japio

Inventors

• 👤 Kunihiko Hirashima

Bibliographic Details