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JPS5592040A Expired / Lapsed JP ⏱️ 0.0 years remaining

Ttl gate circuit

Assignee: Fujitsu Ltd
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Filing: 1978-12-29
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Granted: —
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Expires: 1998-12-29
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Abstract

Abstract PURPOSE:To make it possible to obtain a high-level output voltage over a prescribed value by separating a pull-up circuit and a pull-down circuit from the input terminal and by operating them independently. CONSTITUTION:Transistor TrQ7 and Q3 are connected in series between power source +VCC and the earth, and signals are supplied to their gates. TrQ3 is emitter-grounded, and the base is connected to the earth through a resistance, etc., and is connected to power source +VCC through TrQ2, and therefore, the pull- down circuit receives one divided input signal IN to turn on and off TrQ3. Meanwhile, TrQ7 has the collector connected to power source +VCC, and the base is connected to power source +VCC through resistance R5, and the base is grounded through TrQ6, and therefore, the pull-up circuit receives the other divided input signal IN to turn on and of TrQ7. As the result, pull-up and pull-down circuits can be operated independently to obtain a high-level output voltage over a prescribed value.

Inventors

  • 👤 Osamu Oba
  • 👤 Norikuni Azuma

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-09 00:30
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/082; H03K19/088

Claims Analysis

Total Claims: 0
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References Cited (Backward Citations)

JPS493288A Cited

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