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JPS558192A Expired / Lapsed JP ⏱️ 0.0 years remaining

Carrier wave extracting circuit

Assignee: NEC Corp
•
Filing: 1978-07-05
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Granted: —
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Expires: 1998-07-05
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Abstract

Abstract PURPOSE:To secure the steady phase detection with the reduced error by obtaining the logic product between the signal obtained by n-multiplication to the received wave of the digital n-phase modulation and the signal formed by delaying the n- multiplied signal by the fixed period. CONSTITUTION:The reception signal entered terminal 601 is n-multiplied through n-multiplication circuit 602 with its irregular pulse removed through irregular pulse removing circuit 607. This signal then undergoes the waveform shaping through slicer 604 after passing through resonator 603 and then changed to the original frequency throuth 1/n-divider 605 to be delivered in the form of the carrier wave free from the phase shift through terminal 606. Circuit 607 gives 2-branching to the signal entered input terminal 701. And one of the branched signals is supplied to logic product circuit 702, and the other signal is supplied also to circuit 702 uia delay line 703 with delay of one cycle of the n-multiplied wave or of the integer- fold amount of one cycle to be delivered to output terminal 704 after removal of the irregular pulse. As a result, the carrier wave can be extracted in a steady way, ensuring the steadey phase detection with the reduced error.

Inventors

  • 👤 Ichiro Takase

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-05 17:18
CPC Classifications
H; H04; H04L; H04L27/00; H04L27/18; H04L27/22; H04L27/227; H04L27/2275; H04L27/2276

Claims Analysis

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References Cited (Backward Citations)

JPS5249756A Cited

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