Semiconductor memory unit

Abstract

Abstract PURPOSE:To increase the input information of a sense amplifier circuit by connecting bit lines, divided into several, to memory cells and by controlling connections between those bit lines and the sense amplifier circuit through switching transistors by a signal corresponding to an address signal. CONSTITUTION:Symmetrical memory cells MC1, MC2... selected by symmetric word lines WL1, WL2... are connected to respectively-divided symmetric bit lines BL1, BL2..., which are symmetrically connected to sense amplifier circuit A in parallel by way of switching transistors Tr5, Tr6... controlled by address signals respectively. Therefore, ones cell MC1, etc., is selected, input information to circuit A is in proprotion to the ratio of storage capacity C1 to the sum of floating capacities C7 and C11, and greater than that when cells are connected in series, so that even if cells would increase in number, the input information applied to the sense amplifier circuit can be increased. Further, the designing of a pattern is simplified because pitches in terms of the pattern designing of the sense amplifier circuit can be increased.

Inventors

• 👤 Toshio Ichiyama
• 👤 Makoto Taniguchi

Bibliographic Details