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JPS5572061A Expired / Lapsed JP ⏱️ 0.0 years remaining

Semiconductor device

Assignee: Mitsubishi Electric Corp
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Filing: 1978-11-25
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Granted: —
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Expires: 1998-11-25
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Abstract

Abstract PURPOSE: To heighten dielectric breakdown voltage between layers, by providing the first layer's bend with a larger inner angle than the right angle at the time when forming a piled amorphous layer to be used for a semiconductor device by providing the second layer's amorphous Si layer on the first layer's amorphous Si layer of bent pattern shape through an insulation layer. CONSTITUTION: When a memory LSI, etc. is prepared, the first layer's amorphous Si layer 3 having a bent pattern shape on an Si substrate 1 and the second layer amorphous Si layer 4 having an equally bent pattern are mutually insulating and buried in an SiO 2 film 2, and thus formed objects are used as No.1 and No.2 MOS transistor's gate electrodes. In this mechanism, an inner angle 5 in the bent of the first layer's amorphous layer 3 is provided with a larger angle than the right angle, that is, 2 chamferred inner angles 5a and 5b are to be 135° each. It is possible to heighten dielectric bearing force between the layers 3 and 4 remarkably. COPYRIGHT: (C)1980,JPO&Japio

Inventors

  • 👤 Natsuo Tsubouchi
  • 👤 Tatsuya Enomoto

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-08 07:32
CPC Classifications
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