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JPS5570059A Expired / Lapsed JP ⏱️ 0.0 years remaining

Semiconductor memory device

Assignee: Mitsubishi Electric Corp
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Filing: 1978-11-20
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Granted: —
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Expires: 1998-11-20
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Abstract

Abstract PURPOSE:To eliminate the unbalance of the reading of 0 and 1, by forming a one transistor-dynamic RAM by means of two layer poly Si, by making up a one layer portion as a condenser electrode and a two layer portion as a gate electrode in a memory and by turning the layer portions the other way in dummy. CONSTITUTION:In a memory cell of a 1MIST+IC dynamic RAM, an n-type bit wire 13 is mounted to a p<->-type substrate 11, the first layer poly Si15 is installed through a thin SiO2 film 14' and used as a condenser electrode and the second layer poly Si16 is disposed onto a SiO2 film 14'' and employed as a gate electrode. In a dummy cell, meanwhile, a n-type bit wire 33 is mounted to a p<->-type substrate 31, the first layer poly Si35, 35' are installed through thin SiO2 films 34'', 34''' and used as gate electrodes and the second poly Si36 is disposed through a SiO2 film 34' and employed as a condenser electrode. Thus, the dummy condenser is easily formed, and the information of 0 and 1 memorized in the memory cell can stably be sensed and can be amplified.

Inventors

  • 👤 Kazuhiro Shimotori
  • 👤 Yasuharu Nagayama
  • 👤 Hideyuki Ozaki

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-01 12:24
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30

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