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JPS5567993A Expired / Lapsed JP ⏱️ 0.0 years remaining

Semiconductor memory unit

Assignee: Fujitsu Ltd
•
Filing: 1978-11-14
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Granted: —
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Expires: 1998-11-14
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Abstract

Abstract PURPOSE: To prevent the access time of RAM from shortening by interposing an amplifier between respective word lines switching transfer gates of RAM composed of silicon sapphire (SOS) MOSFETs. CONSTITUTION: Random-access memory RAM consists of FF1 of SOS CMOSFETs 1a and 1b and trasfer gates 2a and 2b of SOS MOSFETs, and respective gates 2a... and 2b... of RAM are simultaneously controlled through work lines 3. Between those lines 3, amplifier 7 composed of two inverters 7a and 7b connected together is interposed and when driving terminal 5 of line 3 is held at a driving potential, the output distribution of inverter 7a decreases gradually by the delay network of RAMs down to a threshold voltage, where inversion is caused to hold momently the output of inverter 7b at the driving potential, thereby making gates 2a and 2b conduct before delaying. Therefore, the access time of RAM never shortens even if the gate insulation film of SOS MOSFET is thinned in order to increase the operation speed of FET. COPYRIGHT: (C)1980,JPO&Japio

Inventors

  • 👤 Nobuo Sasaki
  • 👤 Yasuo Kobayashi
  • 👤 Takashi Iwai
  • 👤 Motoo Nakano

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-01 23:57
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/413; G11C11/417; G11C11/418; G11C11/401; G11C11/4063; G11C11/407; G11C11/408; G11C11/4085; G11C11/412; G11C5/00; G11C5/06; G11C5/063; G11C8/00; G11C8/08; H; H10; H10B; H10B10/00; H10B10/12; H10B10/125

Claims Analysis

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References Cited (Backward Citations)

JPS5329240B2 Cited
JPS5325324A Cited

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