Manufacture of semiconductor device

Abstract

Abstract PURPOSE: To increase voltage resistance, by having lowered the impurity concentration of the region sandwiching a gate electrode on a semiconductor substrate constituting SOS FET, and providing here high-concentration source and drain regions of opposite conduction type. CONSTITUTION: Si epitaxial layer 1 is grown on sapphire substrate 20, and by etching, the thickness of areas 1a, 1b of the element-forming region is reduced by half. Next, SiO 2 film 2 and Si 3 N 4 film 3 are laminated on the element-forming region only. With this used as mask, heat treatment is operated, and layer 1 which is exposed in areas 1a and 1b is changed into SiO 2 , and its volume is expanded and its surface is made flat. Subsequently, films 2 and 3 are removed and exposed layer 1 is changed into p-type by ion injection; gate SiO 2 film 6 and polycrystalline Si layer 7 are grown on its surface. Next, using resist film 8 as mask, layer 7 is etched and is retained as gate electrode 7. Film 8 is removed, p - -type regions 13, 15 are provided on both sides of electrode 7 in layer 1 by ion injection, and here n + -type source and drain regions 11, 12 are formed. COPYRIGHT: (C)1980,JPO&Japio

Inventors

• 👤 Nobuo Sasaki
• 👤 Yasuo Kobayashi
• 👤 Takashi Iwai
• 👤 Motoo Nakano

Bibliographic Details