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JPS5557960A Expired / Lapsed JP ⏱️ 0.0 years remaining

Debugging system

Assignee: Nissin Electric Co Ltd
•
Filing: 1978-10-25
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Granted: —
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Expires: 1998-10-25
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Abstract

Abstract PURPOSE: To simplify interruption constitution by using a signal, based on the output of an address comparator circuit, as a bus charnge-over signal. CONSTITUTION: While CPU11 is executing a program, address comparator circuit 15 makes a comparison between the address value of 1st address bus 14a and a break point and when the both agree each other, coincidence output (a) is outputted make 1st tri-state buffer circuit 19 high in impedance and 1st and 3rd data buses 14a and 14b are mutually insulated to make 2nd tri-state buffer circuit 19 conductive, so that 2nd and 3rd data buses 14b and 14c will mutually connected. Therefore, CPU11 having attained access to memory 12 starts executing the contents of memory address jumping memory 20. At the same time as access to memory 20, CPU11 sends a reset signal C to latch circuit 16 to changing a bus to the original one and then executes the contents of memory 12. COPYRIGHT: (C)1980,JPO&Japio

Inventors

  • 👤 Soji Nishimura

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-02 21:19
CPC Classifications
—

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