JPS555544A
Expired / Lapsed
JP
⏱️ 0.0 years remaining
Timing pulse generation circuit
Assignee: Panasonic Electric Works Co Ltd
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Filing: 1978-06-28
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Granted: —
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Expires: 1998-06-28
Abstract
Abstract PURPOSE:To produce an arbitrary pulse width, delay time and pulse pattern, by outputting the pattern set to the shift register in synchronizing with the clock. CONSTITUTION:When the signal is ''1'' after the desired pattern is set in the switch by operating the dip switch 2, ''1'' is inputted to the NAND gates 61 to 64 via the AND gate 7 to open the gate and to write in desired pattern to the flip flops D1 to D4 constituting the registers. The pattern written in is shifted when the clock pulse is fed to the input terminal CE of the flip flop to output as Sout.
Inventors
- 👤 Hidenori Yamazaki
- 👤 Noboru Uechi
Bibliographic Details
Application Number
—
Jurisdiction
JP
Data Source
google_patents
Last Synchronized
2026-10-30 23:25
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/78
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