Timing information transmission system

Abstract

Abstract PURPOSE: To reduce greatly the number of connection lines between respective blocks of a main circuit and slave circuit by expressing timing information by signals of flag bits and address bits characteristic to each slave-circuit block and by multiplexing this signal in series. CONSTITUTION: Digital composite circuit 1 consists of main-circuit block 3 including address-signal generating circuit 2 and slave-circuit blocks 4a, 4b,... performing fixed operations by commands from the main circuit. Circuit 2 sends clock signal S 1 and address signal S 2 synchronizing with it to decoder circuits 7a, 7b... via bus lines 5 and 6. Initial bit F of signal S 2 is a flag bit, which is invariably "1", and bits (a) to (e) are address bits, which have the inserted characteristic addres codes supplied to respective blocks 4a, 4b.... Respective words constituting signal S 2 are multiplexed in series at interval (t 1 ) of time through line 6. Signal S 2 is decoded by circuits 7a and 7b, which output one of access signal S 3a , S 3b ..., thereby making a corresponding circiut among access-attained circuit 8a, 8b.... COPYRIGHT: (C)1980,JPO&Japio

Inventors

• 👤 Masao Yamazawa
• 👤 Takao Moriya
• 👤 Toyoji Nakazawa

Bibliographic Details