Read control circuit for memory unit

Abstract

Abstract PURPOSE:To increase the read speed of a memory by attaining selective access to a memory where odd and even-address data have been stored by the least significant bit (LSB) of an address signal. CONSTITUTION:By read clock S1 and count-up signal S2, LSB of an address signal from register 3 is updated in each period of clock S1 and remaining bits are in every other bit; and even and odd memories where even and odd-address data have been stored are selected by turns by LSB and that after passing through inverter 6. On the other hand, bits other than LSB from register 3 are delayed by one period of clock of clock S1 by the AND output of AND gate 5 receiving clocks S1 and S2 and then transferred to register 4. Therefore, memories 1 and 2 can be read at a high speed by addressing to memories 1 and 2 by registers 3 and 4 which output addresses in a shorter time than the access time of memories 1 and 2.

Inventors

• 👤 Tadashi Hiura
• 👤 Masahisa Yano

Bibliographic Details