Memory unit

Abstract

Abstract PURPOSE: To realize high-speed operation by limiting a difference in potential between logical levels of sense nodes. CONSTITUTION: Once high level logic 1 of memory cell 50 is read out, 1st control transistor QCH becomes low in gate potential level and 2nd control transistor QCL low in gate potential level to conduct, stopping the potential of sense node 10 from exceeding a fixed value. When low-level logic 0 is read out, 1st transistor QCH conducts to the contrary, thereby stopping the potential of sense node 10 from decreasing below a fixed value. The charge-discharge time of node 10 can therefore be shortened by limiting the amplitude of the potential of sense node 10. COPYRIGHT: (C)1980,JPO&Japio

Inventors

• 👤 Yoshinari Kitamura

Bibliographic Details