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JPS5517871A Expired / Lapsed JP ⏱️ 0.0 years remaining

Semiconductor memory device

Assignee: Toshiba Corp
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Filing: 1978-07-25
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Granted: —
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Expires: 1998-07-25
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Abstract

Abstract PURPOSE:To improve refresh effects by controlling the refresh of a memory through a diode. CONSTITUTION:When node N3 of a memory cell stores a low level, MOS transistor T3 is turned off, and the low level is stored in node N3 to refresh practically the memory cell as long as MOS transistor T3 is turned off. When storage of node N3 becomes high-level, transistor T3 is turned on, and signal line R to which capacity Ba is connected becomes high-level to increase the level of node N3, and node N4 is precharged to make Shottky diode D reverse bias-state. When the signal level of line R becomes low-level, potential lowering of node N3 is compensated through diode D where the reverse bias state is released, so that refresh effects can be improved by the small-loss diode in comparison with the case where a transistor is used.

Inventors

  • 👤 Yasoji Suzuki
  • 👤 Kiyobumi Ochii

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-02 14:34
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/402

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