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JPS5514718A Expired / Lapsed JP ⏱️ 0.0 years remaining

Mos transistor circuit

Assignee: Seiko Epson Corp
•
Filing: 1978-07-17
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Granted: —
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Expires: 1998-07-17
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Abstract

Abstract PURPOSE:To secure the variable amplification factor for the amplifier by applying the input signal to one side of the amplifier and the signal voltage-divided between the input signal and the specified voltage level to the other side respectively when the differential amplifier is constituted with MOSFET. CONSTITUTION:The amplifier consists of P-channel MOSFET1 and 2 plus N- channel MOSFET3-5, and plus power source VDD and minus power source VSS are connected to the side of FET1 and 2 and the side of FET5 each. At the same time, bias level VS is applied to FET1 and 2 with VS' applied FET5 respectively. Furthermore, input VIN to be applied to FET3 and bias level VG are connected via resistance 8, and output Vout1 and Vout2 are drawn out from FET1 and 4 respectively. In such constitution, the resistance 8 value is controlled by the output of FET4. As a result, input VIN turns to the voltage-divided signal, thus securing the varying amplification factor for the amplifier.

Inventors

  • 👤 Yasutaka Nakasaki

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-10-31 08:53
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/45

Claims Analysis

Total Claims: 0
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References Cited (Backward Citations)

JPS4421049Y1 Cited

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