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JPS55140262A Expired / Lapsed JP ⏱️ 0.0 years remaining

Semiconductor device

Assignee: Nippon Gakki Co Ltd
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Filing: 1979-04-19
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Granted: —
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Expires: 1999-04-19
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Abstract

Abstract PURPOSE:To simplify the fabricating steps of a semiconductor device and provide high integrity thereof by forming a reverse conducting type region at the gate region of a vertical junction type FET in the gate region when forming an insulating gate type FET and forming double diffusion type gate region disposed with gate electrodes partially on the gate region. CONSTITUTION:A silocon substrate 10 is formed with an n<+>-type layer 12 and an n<->-type layer 14 epitaxially grown thereon, and two p<+>-type region 16 consisting of a gate region of a vertical junction type FET or a SIT element Q2 and a substrate region of an insulating gate type FET element Q1 is diffused at both sides of the center 14A of the layer 14. Then, the n<+>-type source region 18 is formed at the elements Q1 and Q2 in the respective regions 16, the portion of the layer 14A interposed with the regions 16 is used as a vertical channel region of the element Q2, and the surface portion 16A between the layer 14A and the region 18 is used as the lateral channel region of the element Q1. Thereafter, an SiO2 gate insulating layer 20 is coated on the entire surface while reducing the thickness thereof on the surface portion 16A, and a gate electrode layer 24 is formed on the layer 14A.

Inventors

  • 👤 Takeshi Matsuyama

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-04 22:07
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/64; H10D30/66; H10D64/00; H10D64/20; H10D64/27; H10D64/311; H10D64/411; H10D64/511; H10D64/514; H10D64/516; H10D84/00; H10D84/80; H10D84/82

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