← Back to Patent Explorer
JPS55100713A Expired / Lapsed JP ⏱️ 0.0 years remaining

Muting circuit

Assignee: Hitachi Ltd
•
Filing: 1979-01-26
•
Granted: —
•
Expires: 1999-01-26
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract PURPOSE:To eliminate a momentary increase in gain at the start of muting, by allowing a current by-pass transistor, constrolled by a mute signal, to operate in its unsaturation range. CONSTITUTION:Input signals (i) and (i ) supplied differentially are inputted to current Miller circuits Q1-Q4. Then, transistors Q10 and Q11 constituting a current by-pass circuit where their collectors are connected direct to emitters of output transistors Q2 and Q4, and forward diodies D1 and D2 which limit base input voltages are provided. Once a mute voltage is inputted, Q10 and Q11 try to conduct through buffer Q12, but since the base voltage is limited through the operation of D1 and D2, a current is absorbed without saturating. No variation in impedance viewed from Q2 and Q4 to Q10 and Q11 is caused, so that the gain of a current Miller circuit will greatly lessen without increasing.

Inventors

  • 👤 Kazuo Watanabe
  • 👤 Masanori Ienaka

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-10-27 11:46
CPC Classifications
H; H03; H03G; H03G3/00; H03G3/20; H03G3/30; H03G3/34

Claims Analysis

Total Claims: 0
No claims parsed yet. Click Sync Now above to re-index claims from Google Patents.

References Cited (Backward Citations)

No citation records indexed.

USPTO Annuity & Maintenance Windows

Maintenance schedule is calculated for granted US utility patents.

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag