← Back to Patent Explorer
JPS5488084A Expired / Lapsed JP ⏱️ 0.0 years remaining

Test method of semiconductor device

Assignee: Fujitsu Ltd
•
Filing: 1977-12-26
•
Granted: —
•
Expires: 1997-12-26
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract PURPOSE: To test LSI with extremely simple measuring unit, by preparing the momory of several bits enabling to write in and readout at a part of the semiconductor chip in advance. CONSTITUTION: The memory 21 enabling write-in and readout is inserted at the space outside the circuit pattern 12. For example, the address input terminals 22-1 and 22-2 and the input and output terminal 23 in 2-bit are available. The driving power supply is in common use with the pattern 12. The address region of 2 2 ways can be desingated with the address input terminal in 2-bit. One address region displays the circuit functional module, and the types of module is discriminated and displayed at the terminal 23 by designating it. The discrimination and display is detected with the tester. Test is conducted through the measurimg pad 13 and when the ranking is determined, write-in is made to other addresses through the write-in range of tester, and this ranked data are read out with the readout transistor as required, and the entire can be processed electrically while coupling one tester to the chip. COPYRIGHT: (C)1979,JPO&Japio

Inventors

  • 👤 Hiromichi Asaoka
  • 👤 Kazuyuki Takano

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-02 17:56
CPC Classifications
—

Claims Analysis

Total Claims: 0
No claims parsed yet. Click Sync Now above to re-index claims from Google Patents.

References Cited (Backward Citations)

No citation records indexed.

USPTO Annuity & Maintenance Windows

Maintenance schedule is calculated for granted US utility patents.

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag