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JPS5466735A Expired / Lapsed JP ⏱️ 0.0 years remaining

Processing method of parallel operation execution for multi-processor

Assignee: Fujitsu Ltd
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Filing: 1977-11-07
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Granted: —
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Expires: 1997-11-07
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Abstract

Abstract PURPOSE: To enable to share the respective processing for the matrix operation, by performing the parallel operation indication in the level of user's program to the slave processor by the master processor. CONSTITUTION: When the processor P7-0 is a master, parallel operation indication is made to the slave SP 7-1 to 7-3 via the communication line 9. At this time, P7-0 sets the start switch information to itself and sets information SS1 to SS3 to each SP. In each SP, the information SS is checked and the initial set from the main memory unit 5 or P7-0 is jumped to the matrix operation program, the processing indicated is executed, and after the execution of processing, the end switch information ES is set to the p7-0, which sets the information of itself. Thus, P7-0 executes the processing corresponded to itself whan all the information ES is set. COPYRIGHT: (C)1979,JPO&Japio

Inventors

  • 👤 Keiichiro Uchida

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-06 17:17
CPC Classifications
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References Cited (Backward Citations)

JPS5199438A Cited

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