Semiconductor memory device

Abstract

Abstract PURPOSE:To make the high-speed reading possible even when the ON current of a memory-cell array is small, by facilitating the discharge by enabling an inverter to perform the reading in a sense operation time to accelerate the potential variation of a common line. CONSTITUTION:Memory-cell array MA is able to make the maximum n-bit connection and to attain the writing to drains of transistors Tr via digit lines d1, d2...dn. Then, digit lines d1, d2...dn are connected to common read line DL via swtiching Trs Q11, Q12...Q1n, and common line Dl is to sense circuit SA via MOSTr Q22. Here, common line DL is provided with inverter circuit I1 and I2, whose outputs are used for controlling Trs Q28 and Q29; and circuit I1 detects the potential variation of common line DL during the sense operation, and by the detection output, the voltage variation of common line DL is accelerated momentarily to facilitate the discharge. Consequently, the high-speed reading can be done even when the ON current of array MA is small.

Inventors

• 👤 Sumio Tanaka

Bibliographic Details