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JPS5451485A Expired / Lapsed JP ⏱️ 0.0 years remaining

Semiconductor device

Assignee: Toshiba Corp
•
Filing: 1977-09-30
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Granted: —
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Expires: 1997-09-30
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Abstract

Abstract PURPOSE:To make the reverse current of the PN junction to about 1/10 using Au, by selecting Pt for the impurity being life time killer and by diffusing it in the semiconductor substrate constituting MOS-IC. CONSTITUTION:The P type well region 32 is formed by diffusion at a given region of the N type Si substrate 31, the N<+> type drain region 34 the same as the N<+> source region 33 is provided, constituting the N channel MOS transistor. The P<+> type source region 35 and the P<+> type drain region 36 are formed by diffusion, constituting the P channel MOS IC, and the entire substrate 31 is covered with the oxide film 37. After that, the Pt layer 38 is evaporated at the rear side of the substrate 31 and Pt layer 38 is diffused at 800 to 1100 deg.C, and the heat treatment at about 500 deg.C for 10 minutes is made under N2 atmosphere. Thus, by diffusing Pt in the substrate 31, the MOS IC increased for the latch up resistant capability can be obtained.

Inventors

  • 👤 Okimitsu Yasuda
  • 👤 Masaaki Ueda

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-03 01:06
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/858

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