← Back to Patent Explorer
JPS54124641A Expired / Lapsed JP ⏱️ 0.0 years remaining

Memory control circuit

Assignee: NEC Corp
•
Filing: 1978-03-20
•
Granted: —
•
Expires: 1998-03-20
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract PURPOSE: To eliminate an initial memory information setting operation by regulating the order of the supply time of plural power sources and stopping to feed power at a power source anomaly time and executing operations after power supply from a write operation to prevent the destruction and the malfunction of a volatile memory element. CONSTITUTION: Power sources 100 and 101 supplied to a memory circuit are monitored individually by monitor circuits 1 and 2 of input power source monitor part 10; and if all inputs are proper, control circuit 4 of power source supply monitor part 11 is set to supply power source 100 to load 9. Feeding state 105 of the load loop and input power source 100 are monitored by comparator 5; and when signal 104 as well as all input state monitor signal 103 are normal, control circuit 7 is set to supply power source 101 to load 9. Then, the load state is monitored by comparator 8, and control circuits 4 and 7 are reset to stop the power supply to load 9 at an anomaly time. COPYRIGHT: (C)1979,JPO&Japio

Inventors

  • 👤 Yutaka Ikeda

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-05 13:21
CPC Classifications
—

Claims Analysis

Total Claims: 0
No claims parsed yet. Click Sync Now above to re-index claims from Google Patents.

References Cited (Backward Citations)

No citation records indexed.

USPTO Annuity & Maintenance Windows

Maintenance schedule is calculated for granted US utility patents.

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag