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JPH10242602A Expired / Lapsed JP ⏱️ 0.0 years remaining

Multilayer printed circuit board and method of manufacturing the same

Assignee: NEC Corp
•
Filing: 1997-03-03
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Granted: —
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Expires: 2017-03-03
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Abstract

Abstract Translated from Japanese (57)【要約】 【課題】 電源ノイズ発生を大幅に低減しうる多層プリ ント基板を提供する。 【解決手段】 信号層5、グランド層6、電源層7が絶 縁層8を介して積層され、電源層7にはインピーダンス 付加回路1が形成されており、さらにこのインピーダン ス付加回路の上下の少なくとも一方に磁性層2が設けら れている。インピーダンス付加回路1の上下に接するよ うにして磁性層2を設けても良く、またインピーダンス 付加回路1とグランド層6間に絶縁層を全く設けない形 態でも良い。さらには、インピーダンス付加回路1上の みならず電源層7上全面に磁性体層2を設けても良い。 (57) [Problem] To provide a multilayer printed circuit board capable of greatly reducing generation of power supply noise. SOLUTION: A signal layer 5, a ground layer 6, and a power supply layer 7 are laminated with an insulating layer 8 interposed therebetween, and an impedance addition circuit 1 is formed on the power supply layer 7, and at least one of upper and lower sides of the impedance addition circuit. Is provided with a magnetic layer 2. The magnetic layer 2 may be provided so as to be in contact with the upper and lower portions of the impedance adding circuit 1, or a configuration in which no insulating layer is provided between the impedance adding circuit 1 and the ground layer 6 may be used. Further, the magnetic layer 2 may be provided not only on the impedance adding circuit 1 but also on the entire surface of the power supply layer 7.

Inventors

  • 👤 Osamu Myoga
  • 👤 修 冥加
  • 👤 Shiro Yoshida
  • 👤 史郎 吉田
  • 👤 Mitsuo Saito
  • 👤 光雄 斉藤
  • 👤 Yuzo Shimada
  • 👤 勇三 嶋田
  • 👤 Hirokazu Toya
  • 👤 弘和 遠矢
  • 👤 Akira Maniwa
  • 👤 亮 馬庭

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-08 00:31
CPC Classifications
H; H05; H05K; H05K1/00; H05K1/02; H05K1/0213; H05K1/0216; H05K1/023; H05K1/0233; H03; H03H; H03H7/00; H03H7/01; H05K1/0296; H05K1/0298; H05K1/16; H05K1/165; H05K2201/00; H05K2201/08; H05K2201/083; H05K2201/086; H05K2201/09; H05K2201/09209; H05K2201/09218; H05K2201/09263

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