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JPH0645441A Expired / Lapsed JP ⏱️ 0.0 years remaining

Wiring route handling method in automatic layout system of integrated circuit

Assignee: Dai Nippon Printing Co Ltd
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Filing: 1992-07-23
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Granted: —
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Expires: 2012-07-23
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Abstract

Abstract PURPOSE:To facilitate efficient utilization of wiring regions and control of wiring routes and wiring patterns by a method wherein dummy cells containing wiring patterns matched with the purpose are provided in the wiring routes and utilized. CONSTITUTION:If the pin 1p of a cell 2a and the pin 2p of a cell 11a are wired with a conventional layer wiring system having aluminum layers 1 and 2, both the pins are connected to each other with a route which passes through channel regions 1c, 3c, 5c and 6c and makes a detour from a dead area 1e having no channel region. Then, dummy cells 1d and 2d in which aluminum layer 2 wiring patterns 12d and aluminum layer 1 wiring patterns 13d are arranged concentrically are provided as wiring passing cells to produce new channel regions 8c, 9c and 11c. Thus, the wiring passes through the channel regions 1c and 8c, the dummy cell 2d and the channel regions 9c, 5c and 6c and a detour wiring can be eliminated. With this constitution, required wiring routes and wiring patterns can be produced.

Inventors

  • 👤 Mie Funato
  • 👤 美恵 船戸

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-08 16:39
CPC Classifications
—

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