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JPH06151702A Expired / Lapsed JP ⏱️ 0.0 years remaining

Multichip module

Assignee: NEC Corp
•
Filing: 1992-11-09
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Granted: —
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Expires: 2012-11-09
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Abstract

Abstract Translated from Japanese (57)【要約】 【目的】基板上に半導体チップを実装したマルチチップ モジュールにおいて、基板面積の縮小化および基板上の 配線長の短縮化を行うことによって、マイクロプロセッ サの高速化を図る。 【構成】基板1に実装されている半導体チップ2、3を 覆うように絶縁層6を設け、絶縁層6の上に第2層目の 半導体チップ4を実装する。この際、第2層目の半導体 チップ4が基板1上の配線層5とコンタクトをとれるよ うに絶縁層6にビアホール7をあけ、絶縁層6上の金属 配線8と導通させる。さらに、この上に前記絶縁層6、 ビアホール7、金属配線8を順次形成し、半導体チップ を複数層に縦積みしてマルチチップモジュールを形成す る。 (57) [Abstract] [Purpose] In a multi-chip module in which a semiconductor chip is mounted on a substrate, the size of the substrate is reduced and the wiring length on the substrate is shortened, thereby increasing the speed of the microprocessor. [Structure] An insulating layer 6 is provided so as to cover the semiconductor chips 2 and 3 mounted on a substrate 1, and a second-layer semiconductor chip 4 is mounted on the insulating layer 6. At this time, a via hole 7 is opened in the insulating layer 6 so that the semiconductor chip 4 of the second layer can make contact with the wiring layer 5 on the substrate 1 and is electrically connected to the metal wiring 8 on the insulating layer 6. Furthermore, the insulating layer 6, The via hole 7 and the metal wiring 8 are sequentially formed, and the semiconductor chips are vertically stacked in a plurality of layers to form a multi-chip module.

Inventors

  • 👤 Takashi Sakai
  • 👤 貴 酒井

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-09 20:33
CPC Classifications
H; H10; H10W; H10W72/00; H10W72/50; H10W72/541; H10W72/5445; H10W74/00

Claims Analysis

Total Claims: 0
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References Cited (Backward Citations)

JPH0529533A Cited
JPH05259376A Cited

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