JPH05335437A
Expired / Lapsed
JP
⏱️ 0.0 years remaining
Semiconductor device
Assignee: NEC Corp
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Filing: 1992-06-04
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Granted: —
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Expires: 2012-06-04
Abstract
Abstract Translated from Japanese (57)【要約】 【目的】実装時のはんだ不良を防止する半導体装置を得 る。 【構成】金メッキやはんだメッキにより、はんだ付性を 良くした端面電極２の中央部から上に、はんだレジスト ４を形成する。 (57) [Abstract] [Purpose] To obtain a semiconductor device that prevents solder defects during mounting. [Structure] A solder resist 4 is formed on the end surface electrode 2 having a good solderability by gold plating or solder plating, from the central portion to the upper portion.
Inventors
- 👤 Osamu Onishi
- 👤 修 大西
Bibliographic Details
Application Number
—
Jurisdiction
JP
Data Source
google_patents
Last Synchronized
2026-11-08 12:06
CPC Classifications
H; H05; H05K; H05K3/00; H05K3/30; H05K3/32; H05K3/34; H05K3/341; H05K3/3431; H10; H10W; H10W72/00; H10W72/851; H10W72/874; H10W72/884
Claims Analysis
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References Cited (Backward Citations)
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