Semiconductor device and manufacturing method
Abstract
Abstract Translated from Japanese (57)【要約】 (修正有) 【目的】 高集積化に対応可能な配線を有する半導体装 置および製造方法を提供することを目的とする。 【構成】 本発明の半導体装置の製造方法は基体上11 に設けられた絶縁膜14に溝16を形成し、この溝の内 壁面に導電層17を形成し、この導電層を成長の核とし て導電性材料を選択的に堆積させて溝内に埋込配線部を 形成する各工程を含む。導電層の形成工程はエッチバッ ク法を用いて行う。 (57) [Summary] (Modified) [Objective] It is an object to provide a semiconductor device having a wiring which can cope with high integration and a manufacturing method. [Structure] A method for manufacturing a semiconductor device according to the present invention is provided on a substrate 11 A groove 16 is formed in the insulating film 14 provided in the groove, a conductive layer 17 is formed on the inner wall surface of the groove, and a conductive material is selectively deposited using this conductive layer as a growth nucleus to be embedded in the groove. Each step of forming the wiring portion is included. The step of forming the conductive layer is performed by using an etch back method.
Inventors
- 👤 Seiji Kamei
- 👤 誠司 亀井
Bibliographic Details
Claims Analysis
Total Claims: 0References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.