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JPH0469765A Expired / Lapsed JP ⏱️ 0.0 years remaining

Parallel computers and processor monitoring control method

Assignee: Fujitsu Ltd
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Filing: 1990-07-10
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Granted: —
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Expires: 2010-07-10
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Abstract

Abstract PURPOSE:To shorten the collection time of data by providing a control means for sending out collection data to a request origin after the other processor sends out data obtained by multiplying the identification number and length of the collection data, and transmitting automatically the collection data against a single transmitting instruction of the collection data. CONSTITUTION:A collection data setting circuit 15 monitors an executing state of the own processor, and stores status information of the processor in a collection data storage part 13. When a host computer HO sends a transmitting instruction of collection data to each processor P0, P1 ..., a data transmission control circuit 11 of each processor monitors the number of data sent to the host computer HO from the other processor, awaits that data is sent by (own identification x data length L), and thereafter, sends out the status information. Accordingly, when a transfer request is outputted only once in the beginning, the host computer HO can receive continuously the data from each processor thereafter. In such a way, the time required for collecting the data is shortened.

Inventors

  • 👤 Sadayuki Kato
  • 👤 定幸 加藤
  • 👤 Hiroaki Ishihata
  • 👤 石畑 宏明
  • 👤 Toshiyuki Shimizu
  • 👤 俊幸 清水

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-06 09:02
CPC Classifications
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