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JPH04240751A Expired / Lapsed JP ⏱️ 0.0 years remaining

Chip carrier

Assignee: NEC Corp
•
Filing: 1991-01-24
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Granted: —
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Expires: 2011-01-24
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Abstract

Abstract PURPOSE:To eliminate application of a stress to the leads of an IC and to obtain a chip carrier having low thermal resistance by providing a groove in which the edge of a cap for sealing the IC is inserted, on a substrate. CONSTITUTION:A groove 11 is previously formed on a part to be adhered with a cap 8 of a substrate 1. The edge of the cap 8 is inserted into the groove 11, and connected by adhesive 10 such as Au/Sn, Sn/Pb, etc. In this case, when a predetermined load is applied from the upper surface of the cap 8, the edge of the cap 8 is inserted to a position meeting the load in the adhesive 10 in the groove 1, and stopped on the way of the depth of the groove 11. Simultaneously, a cap between the cap 8 and an IC 5 is formed in a stable state.

Inventors

  • 👤 Hikari Kimura
  • 👤 光 木村

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-10 01:44
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/117

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