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JPH04117136A Expired / Lapsed JP ⏱️ 0.0 years remaining

Capacitor bank switching unit

Assignee: Toshiba Corp
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Filing: 1990-09-04
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Granted: —
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Expires: 2010-09-04
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Abstract

Abstract PURPOSE:To suppress influence of prearc and overcurrent onto the interrupting performance at the time of throw-in by throwing in one phase earlier by a predetermined time than two other phases with no-load and interrupting one phase out of three phases at first. CONSTITUTION:When a throw-in command is provided from a command circuit 9 to a switching unit 7 based on a phase detection output provided from a phase detecting circuit 8, phase A main contact is thrown in at first. At the time of interruption, the command circuit 9 provides an interruption command having a phase controlled to open the phase A contact of the switch unit 7 and phase A is interrupted at first zero point followed by interruption of two other phases with 1/4 cycle time lag. Since phase A is thrown in with no-load, prearc or overcurrent arc is not produced at the time of throw-in and thereby the contact is not damaged. Consequently, influence of withstand voltage drop of switching unit due to prearc or overcurrent at the time of throw-in can be suppressed.

Inventors

  • 👤 Matsuo Matsuda
  • 👤 松田 松雄
  • 👤 Kunio Yokokura
  • 👤 邦夫 横倉

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-03 10:11
CPC Classifications
F; F02; F02B; F02B75/00; F02B75/02; F02B2075/022; F02B2075/027; Y; Y02; Y02E; Y02E40/00; Y02E40/30

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