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JPH0344779A Expired / Lapsed JP ⏱️ 0.0 years remaining

Pattern recognizing processor

Assignee: NEC Corp
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Filing: 1989-07-12
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Granted: —
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Expires: 2009-07-12
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Abstract

Abstract PURPOSE:To effectively recognize a pattern by applying a highly efficient pipeline process and a parallel process to perform a space filtering operation, a matrix arithmetic operation, etc., at a high speed. CONSTITUTION:A 2-port memory 10 is prepared together with a dictionary memory 11, a shift arithmetic part 12, an ALU13, and a multiplier/adder 14 respectively in a module. These module elements are actuated in a pipeline process so that the space filtering and matrix arithmetic operations are processes at a high speed with use of the parallelism. Therefore the memory 10 can carry out the reading and writing operations independently of each other. Thus a memory access never bottlenecks the processing speed even though the data receiving the frequent accesses are stored in the memory 10. Furthermore the part 12 performs a normal barrel shift and also segments a noted and nearby picture elements out of a binary picture. In such a constitution, a pattern is recognized with high efficiency.

Inventors

  • 👤 Takeshi Kamimura
  • 👤 健 上村

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-09 15:43
CPC Classifications
—

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