Scan register

Abstract

Abstract PURPOSE:To observe a large number of signals by providing a master latch circuit equipped with serial and parallel input terminals following to a first phase clock and a first strobe, respectively, and a slave latch circuit of similar configuration. CONSTITUTION:Serial data from the serial input terminal 3 is latched with the master latch circuit 21 via a transistor(TR) 1a turned on with the first phase clock phi1 of a scan register, and is latched with the slave latch circuit 22 via a TR 1b turned on with a second phase clock phi2, then, each one bit is outputted. Meanwhile, parallel data from the parallel input terminal 5a is latched with the circuit 21 via a TR 1c turned on with a first strobe signal STB1, and similarly, each one bit is outputted via the circuit 22. Meanwhile, when a TR 1d is turned on with a second strobe signal STB2, the parallel data from the parallel input terminal 5b is latched with the circuit 22, and after that, each one bit is outputted similarly, therefore, observation data can be doubled compared with a case where no parallel data is latched with the circuit 22.

Inventors

• 👤 Hideshi Maeno
• 👤 秀史 前野

Bibliographic Details